1. Field of the Invention
The present invention relates to a structure and a process of a semiconductor. More particularly, the present invention relates to a structure and a process of metal interconnects.
2. Description of the Related Art
After semiconductor fabrication processes reach to a deep sub-micron generation, integration of integrated circuit devices has been greatly enhanced. Deep sub-micron processes, however, has encountered certain problems arising from characteristics of the devices and properties of the materials. Certain characteristics, such as the resistance of the material and electromigration resistivity of aluminum interconnects, are unable to meet the needs of the deep sub-micron processes, which represents one of the pressing problems that need to be solved for fabricating integrated circuits.
In processes of fabricating integrated circuits, technologies of using aluminum to form metal interconnects have become rather mature. In a deep sub-micron process of semiconductor fabrication, however, copper is often used in place of aluminum to form interconnects. This is because copper has an electromigration resistivity 30 to 100 times higher than that of aluminum, a dielectric resistivity 10 to 20 times lower than that of aluminum, and an electric resistivity 30% lower than that of aluminum. Thus, the formation of inter-metal dielectrics by using copper to form metal interconnects in company with use of a material with low dielectric constant (low K) inter-metal can effectively lower resistivity-capacitance delay (RC delay) and increase elelectromigration resistivity.
Referring to FIG. 1, since copper is not easy to be etched, metal interconnects using copper are mostly fabricated by using a method of damascene. In other words, as shown in FIG. 1, a substrate 100 having many preformed devices (not shown) thereon is first provided. A dielectric layer 102a is then formed over the substrate 100 to cover the foregoing devices. The dielectric layer 102a has a damascene opening 108a of a wiring region for connecting with the substrate 100. In the damascene opening 108a is formed a barrier layer 104a, and subsequently a copper metal layer 110a to fill in the damascene opening 108a. The excess portion of the copper metal layer 110a that is outside of the damascene opening 108a is removed through a chemical mechanical polishing method. Over the dielectric layer 102a and the copper metal layer 110a, another dielectric layer 102b is formed having a damascene opening 108b for connecting with the copper metal layer 110a. A barrier layer 104b is formed in the damascene opening 108b, and then a copper metal layer 110b is filled into the damascene opening 108b. Further, the excess portion of the copper metal layer 110b that is outside of the damascene opening 108b is removed to form a structure of metal interconnects.
However, since copper is easy to be oxidized, in the foregoing fabrication processes of a damascene structure, copper oxide is easily formed on the surface of the copper metal layers 110a/110b, which increases electric resistivity of the copper metal layers 110a/110b, and lowers efficiency of the metal interconnects. In addition, copper is a relatively soft metal and the copper oxide formed on the surface of the copper is rather loose, and thus the surface properties of copper are difficult to be controlled, which will induce formation of undercut profile on the copper metal layers 110a/110b, as shown at A and B in FIG. 1, during a process of wet etching or wash with a solvent. Moreover, the formation of copper oxide on the surface of the copper metal layers 110a/110b may also have negative effects to adhesion between the copper metal layers 110a/110b and the barriers layers 104a/104b. 